The present invention is directed to a semiconductor device and method of assembling semiconductor devices from a lead frame and power bar that are adaptable to different package designs.
Lead frames utilizing power bars are typically designed to meet specific integrated circuit (IC) configurations. Thus, such lead frames are specific in application and not generally adaptable to different device specifications. For example, devices with different power pad locations require new lead frame designs. Design and tooling costs, and ultimately unit costs, become higher as a result of the need for specific lead frame configurations. Individualized power bar designs also limit the ability to reuse technology, handicap corporate complexity reduction, and prohibit economy of scale in purchasing. This leads to lost opportunities to save costs.
The current lead frame and power bar designs also pose an issue with the advancement of integrated circuit packaging. For example, quad-flat packaging (QFP) has the lowest cost per input/output (I/O) pin in package platforms, and is therefore used in as many new devices as possible. However, the number of signal, power, and ground I/O pins continues to rise with each generation of IC. Unfortunately, the QFP lead frame designs have not advanced at the same rate with I/O pin demand. If this trend continues, newer generation ICs will be forced into higher cost platforms. One issue with conventional lead frame/power bar designs is that the power bar relies on the sacrifice of usable inner leads for structural support and electrical connectivity.
It is therefore desirable to provide a lead frame design utilizing power bars that is adaptable for use with numerous types of IC configurations and pins and also does not sacrifice inner signal leads.